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Predictive Physical Simulation of III/V Quantum-Well MISFETs for Logic Applications


Z. Stanojevic, M. Karner, M. Aichhorn, F. Mitterbauer, V. Eyert, C. Kernstock, and H. Kosina

2015 45th European Solid State Device Research Conference (ESSDERC)

We present a simulation modeling chain for nano-scaled III/V quantum-well MISFETs. Our methods are based on physical rather than empirical modeling, which allows to obtain predictive simulation results with very few fitting parameters. We use a recent InGaAs-based technology from Intel [1] to validate our simulation results which show excellent agreement with measured capacitance and conductance curves. We further evaluate the properties of a 60 nm long InGaAs quantum-well transistor, finding a sub-threshold slope of 73.5 mV/dec and a DIBL of 103.8 mV/V. A fast numerical computational framework ensures high modeling flexibility; at the same time execution times are kept short making our approach an ideal replacement for empirical device modeling which is still pervasive in TCAD.

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